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MC100EP16VC 3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output
The EP16VC is a differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain and enable output. The EP16VC provides an EN input which is synchronized with the data input (D) signal in a way that provides glitchless gating of the QHG and QHG outputs. When the EN signal is LOW, the input is passed to the outputs and the data output equals the data input. When the data input is HIGH and EN goes HIGH, it will force the QHG LOW and the QHG HIGH on the next negative transition of the data input. If the data input is LOW when the EN goes HIGH, the next data transition to a HIGH is ignored and QHG remains LOW and QHG remains HIGH. The next positive transition of the data input is not passed on to the data outputs under these conditions. The QHG and QHG outputs remain in their disabled state as long as the EN input is held HIGH. The EN input has no influence on the Q output and the data input is passed on (inverted) to this output whether EN is HIGH or LOW. This configuration is ideal for crystal oscillator applications where the oscillator can be free running and gated on and off synchronously without adding extra counts to the output. The VBB/D pin is internally dedicated and available for differential interconnect. VBB/D may rebias AC coupled inputs. When used, decouple VBB/D and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 1.5 mA. When not used, VBB/D should be left open. The 100 Series contains temperature compensation.
http://onsemi.com MARKING DIAGRAMS*
8 8 1 SO-8 D SUFFIX CASE 751 KEP66 ALYW 1 8 8 1 TSSOP-8 DT SUFFIX CASE 948R 1 KP66 ALYW
K = MC100 A = Assembly Location L = Wafer Lot Y = Year W = Work Week *For additional information, see Application Note AND8002/D
* * * * *
* * QHG Output Will Default LOW with D Inputs Open or at VEE * VBB Output
310 ps Typical Prop Delay Q, 380 ps Typical Prop Delay QHG, QHG Gain > 200 Maximum Frequency > 3 GHz Typical PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State
ORDERING INFORMATION
Device MC100EP16VCD MC100EP16VCDR2 MC100EP16VCDT Package SO-8 SO-8 TSSOP-8 Shipping 98 Units/Rail 2500 Tape & Reel 100 Units/Rail
MC100EP16VCDTR2 TSSOP-8 2500 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2003
1
September, 2003- Rev. 2
Publication Order Number: MC100EP16VC/D
MC100EP16VC
Q
1
8
VCC
PIN DESCRIPTION
PIN FUNCTION ECL Data Input ECL Data Output ECL High Gain Data Outputs ECL Enable Input Reference Voltage Output / ECL Data Input Positive Supply Negative Supply
D
2
7
QHG
D* Q QHG, QHG
VBB/D
3 OE
6
QHG
EN* VBB/D VCC
LEN VBB EN 4
Q
LATCH D
5
VEE
VEE
* Pins will default LOW when left open.
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW N/A > 4 kV > 200 V > 2 kV Level 1 UL 94 V-0 @ 0.125 in 167 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 LFPM 500 LFPM std bd 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 8 SOIC 8 SOIC 8 SOIC 8 TSSOP 8 TSSOP 8 TSSOP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 6 -6 6 -6 50 100 1.5 -40 to +85 -65 to +150 190 130 41 to 44 185 140 41 to 44 265 Units V V V V mA mA mA C C C/W C/W C/W C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
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MC100EP16VC
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 5) Input HIGH Current Input LOW Current D 0.5 Min 25 2105 1305 2075 1355 1725 2.0 1825 -40C Typ 36 2230 1430 Max 45 2355 1555 2420 1675 1925 3.3 150 0.5 Min 30 2105 1305 2075 1355 1700 2.0 1800 25C Typ 40 2230 1430 Max 50 2355 1555 2420 1675 1900 3.3 150 0.5 Min 32 2105 1305 2075 1355 1675 2.0 1775 85C Typ 42 2230 1430 Max 52 2355 1555 2420 1675 1875 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 4. All loading with 50 W to VCC-2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 8) Input HIGH Current Input LOW Current D 0.5 Min 25 3805 3005 3775 3055 3425 2.0 3525 -40C Typ 36 3930 3130 Max 45 4055 3255 4120 3375 3625 5.0 150 0.5 Min 30 3805 3005 3775 3055 3400 2.0 3500 25C Typ 40 3930 3130 Max 50 4055 3255 4120 3375 3600 5.0 150 0.5 Min 32 3805 3005 3775 3055 3375 2.0 3475 85C Typ 42 3930 3130 Max 52 4055 3255 4120 3375 3575 5.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 7. All loading with 50 W to VCC-2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9)
Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 10) Output LOW Voltage (Note 10) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 11) Input HIGH Current Input LOW Current D 0.5 Min 25 -1195 -1995 -1225 -1945 -1575 -1475 VEE+2.0 -40C Typ 36 -1070 -1870 Max 45 -945 -1745 -880 -1625 -1375 0.0 150 0.50 Min 30 -1195 -1995 -1225 -1945 -1600 -1500 VEE+2.0 25C Typ 40 -1070 -1870 Max 50 -945 -1745 -880 -1625 -1400 0.0 150 0.5 Min 32 -1195 -1995 -1225 -1945 -1625 -1525 VEE+2.0 85C Typ 42 -1070 -1870 Max 52 -945 -1745 -880 -1625 -1425 0.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 W to VCC-2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC100EP16VC
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 12)
-40C Symbol fmax tPLH, tPHL Characteristic Maximum Frequency (See Figure 2 Fmax/JITTER) Propagation Delay (Differential) Q (Differential) QHG, QHG (Single-Ended) Q (Single-Ended) QHG, QHG Setup Time Hold Time Duty Cycle Skew (Note 13) RMS Random Clock Jitter (See Figure 2 Fmax/JITTER) Input Voltage Swing (Differential Configuration) Output Rise/Fall Times (20% - 80%) HG Q Q QHG, QHG 25 150 200 70 EN = L to D EN =H to D EN = L to D EN =H to D 200 250 250 300 50 100 100 50 Min Typ >3 280 360 330 410 15 60 50 15 5.0 0.2 800 800 300 130 20 <1 1200 1200 400 220 25 150 250 80 350 450 400 500 250 300 300 350 50 100 100 50 Max Min 25C Typ >3 310 380 360 430 5 40 40 20 5.0 0.2 800 800 350 150 20 <1 1200 1200 450 240 25 150 250 100 400 500 450 550 275 325 325 375 50 100 100 50 Max Min 85C Typ >3 340 430 390 480 18 10 5 20 5.0 0.2 800 800 350 170 20 <1 1200 1200 500 270 425 525 475 575 Max Unit GHz ps
tS tH tSKEW tJITTER VPP tr tf
ps ps ps ps mV ps
12. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V. 13. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs.
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MC100EP16VC
Single-Ended Input
900 800 VOUTpp (mV) 700 600 500 400 300 200 100 0 9 8 7 6 5 4 3 2 1 JITTEROUT ps (RMS) JITTEROUT ps (RMS)
900 800 VOUTpp (mV) 700 600 500 400 300 200 100 0
EEEE E EEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEE EEEEEE EEEEEE
0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (MHz)
Figure 2. Fmax/Jitter for QHG, QHG Output
9 8 7 6 5 4 3 2 1
EEEEEEE EEEEEEEEEEEEEEEE E EE EEEEEEEEEEEEEEEE E EE EEEEEEE EE EEEEEEE
0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (MHz)
Figure 3. Fmax/Jitter for Q Output
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MC100EP16VC
Differential Inputs
900 800 VOUTpp (mV) 700 600 500 400 300 200 100 0 9 8 7 6 5 4 3 2 1 JITTEROUT ps (RMS) JITTEROUT ps (RMS)
900 800 VOUTpp (mV) 700 600 500 400 300 200 100 0
EEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEE EE EE
0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz)
Figure 4. Fmax/Jitter for QHG, QHG Output
9 8 7 6 5 4 3 2 1
EEEEE EEEEEEEEEEEEEEEEEE E EEEEEEEEEEEEEEEEEEEE E EEEEEEE EEEEEEE
0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz)
Figure 5. Fmax/Jitter for Q Output
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MC100EP16VC
Q Driver Device Q 50 W 50 W
D Receiver Device D
V TT V TT = V CC - 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1504 AN1568 AN1650 AN1672 AND8001 AND8002 AND8009 AND8020 - - - - - - - - - - - ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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MC100EP16VC
PACKAGE DIMENSIONS
-X- A
8 5
SO-8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-07 ISSUE AA
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDAARD IS 751-07 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
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MC100EP16VC
PACKAGE DIMENSIONS
TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A
8x
K REF 0.10 (0.004)
M
0.15 (0.006) T U
S 2X
TU
S
V
S
L/2
8
5
L
1 PIN 1 IDENT 4
B -U-
0.25 (0.010) M
0.15 (0.006) T U
S
A -V-
F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_
C 0.10 (0.004) -T- SEATING
PLANE
D
-W- G DETAIL E
DIM A B C D F G K L M
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MC100EP16VC
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PUBLICATION ORDERING INFORMATION
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MC100EP16VC/D

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